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March 2014 Volume.1 Issue.1
 
An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic
International Journal of Advanced Computing and Communication Systems (IJACCS)
© 2014 by IJACCS Journal
Volume - 1, Issue - 1
Year of Publication: March 2014
Author's: Kavinmalar. P, B.Jaishankar Paper ID: IJEEE140
 
Full Text
 
Citation
Kavinmalar. P, B.Jaishankar. An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic. International Journal of Advanced Computing and Communication Systems (IJACCS). Volume.1 Issue.1 March 2014.
 
Abstract
Power consumption has become a significant concern in the design of digital integrated circuits. It is necessary to provide low power and 7high performance system. An improved fine grained power gating technique is presented in this paper. This work mainly focused on obtaining low power by implementing asynchronous logic. Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. It represents an important design methodology in recent deep sub-micron technologies. High leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation as threshold voltage, channel length, and gate oxide thickness are reduced. Power gating is one of the most effective techniques for leakage reduction. In the proposed work, each pipeline stage in the circuit is comprised of logic gates, which implements the logic function and a handshake controller. The power to the logic blocks are controlled and supplied by the handshaking controllers. The work measures and compares the power consumption, area and delay of a 4 bit traditional Array multiplier with the proposed power gated Array multiplier using DSCH tool.
 
References
  1. [1]Chang.M.C, and Chang.W "Asynchronous Fine-Grain Power-Gated Logic" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, June 2013 1143. [2]Lin.T, Chong.K.S, Gwee.B.H, and Chang.J.S, “Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic,” in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp. 3162–3165. [3]Ortega.C, Tse.J, and Manohar.R, “Static power reduction techniques for asynchronous circuits,” in Proc. IEEE Symp. Asynchronous Circuits Syst., May 2010, pp. 52–61. [4]Thonnart.Y, Beigne.E, Valentian.A, and Vivet.P, “Automatic power regulation based on asynchronous activity detection and its application to ANOC node leakage reduction,” in Proc. IEEE Symp. Asynchronous Circuits Syst., Apr. 2008, pp. 48–57. [5]Usami.K, Shirai.T, Hashida.T, Masuda.H, Takeda.S, Nakata.M, Seki.N, Amano.H, Namiki.M, Imai.M, M. Kondo, and H. Nakamura, “Design and implementation of fine-grain power gating with ground bounce suppression,” in Proc. 22nd Int. Conf. VLSI Design, 2009, pp. 381–386. [6]Aziz, S.M.; Sch. of Electr. & Inf. Eng., Univ. of South Australia, Mawson Lakes, SA, Australia ; Sicard, E. ; Ben Dhia, S."Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools “Education, IEEE Transactions on (Volume:53, Issue: 4),03 November 2009.
 
Keywords
Asynchronous logic, power gating, low power.
 

 

 
 
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