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March 2014 Volume.1 Issue.1
An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic
International Journal of Advanced Computing and Communication Systems (IJACCS)
© 2014 by IJACCS Journal
Volume - 1, Issue - 1
Year of Publication: March 2014
Author's: Kavinmalar. P, B.Jaishankar Paper ID: IJEEE140
Full Text
Kavinmalar. P, B.Jaishankar. An Improved Power Gating Technique for Low Power Circuits Using Asynchronous Logic. International Journal of Advanced Computing and Communication Systems (IJACCS). Volume.1 Issue.1 March 2014.
Power consumption has become a significant concern in the design of digital integrated circuits. It is necessary to provide low power and 7high performance system. An improved fine grained power gating technique is presented in this paper. This work mainly focused on obtaining low power by implementing asynchronous logic. Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. It represents an important design methodology in recent deep sub-micron technologies. High leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation as threshold voltage, channel length, and gate oxide thickness are reduced. Power gating is one of the most effective techniques for leakage reduction. In the proposed work, each pipeline stage in the circuit is comprised of logic gates, which implements the logic function and a handshake controller. The power to the logic blocks are controlled and supplied by the handshaking controllers. The work measures and compares the power consumption, area and delay of a 4 bit traditional Array multiplier with the proposed power gated Array multiplier using DSCH tool.
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Asynchronous logic, power gating, low power.


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